In a recent unpublished German patent application, a two flip-flop pipeline structure for a data buffer is proposed. The input data, which may actually be address data in a memory system, are clocked into the first flip-flop (more generally a “data register”) with the system input clock, and from the output of the second flip-flop are clocked into the second flip-flop with an internal clock signal provided by a phase locked loop (PLL), the reference input of which receives the system input clock. The PLL also provides internal clock signals to data destination devices, e.g., RAM modules in a memory system. With such a two flip-flop pipeline structure, the propagation delay time (tpd) from the system clock input to the clock outputs is controlled by the PLL. Unless the PLL includes some phase adjustment means, the propagation delay time will be fixed and determined by the clock frequency. For the proper functionality of the structure, the phase of the internal clock at the second flip-flop must be adjusted so that even under the worst case conditions no violation of the setup/hold timing occurs, thus avoiding that the wrong data are stored in the second flip-flop. In view of this requirement, it would be safe to move the phase of the internal clock at the second flip-flop sufficiently away from the phase of the clock at the first flip-flop so as to cover the worst case condition. But this would also produce the longest propagation delay time.